Senior ASIC Timing & Design Engineer; Equity
Listed on 2026-10-07
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Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer
NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Engineer to join our Networking Silicon team in Westford. You will drive timing closure for high-frequency DPUs and SoCs from RTL to GDS2, analyzing constraints and optimizing performance, power, and area.
Ideal candidates hold a BS or MS in Electrical/Computer Engineering with 4–8+ years in synthesis, STA, ECOs, and physical design, and are proficient with Prime Time or Tempus and scripting in Python/Tcl.
We would love to welcome a new Senior ASIC Timing & Design Engineer (Equity) to our organisation in Westford, MA, United States.
Our organisation is growing, and we are hiring a Senior ASIC Timing & Design Engineer (Equity) in Westford, MA, United States.
This role is for the Senior ASIC Timing & Design Engineer (Equity) role at NVIDIA Corporation.
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