Space FPGA Engineering Internship - HDL Design
Listed on 2026-10-07
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Engineering
Electronics Engineer
Cesium Astro is seeking Summer 2027 FPGA development interns to help design HDL-level FPGA systems for satellite communication.
You will work with engineers on design, verification, and deployment, including high-speed interfaces, multiple clock domains, and testing with lab instruments. Excellent communication required; on-site at our Colorado facilities; current students in EE/CE with GPA 3.5+ encouraged to apply.
We are currently recruiting a Space FPGA Engineering Internship - HDL Design for our team in Westminster, CO, United States.
All applications are reviewed carefully by our team.
The position is based in Westminster, CO, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 22.000 - 29.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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