Product Engineer; DFT in-system test

Product Engineer (DFT in-system test)

Join to apply for the Product Engineer (DFT in-system test) role at Siemens EDA (Siemens Digital Industries Software).

• Company:
  Siemens EDA
• Job Title:
  
  Product Engineer (DFT in-system test)
• Job Reference #: 487865
• Location:
  
  Wilsonville, OR

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

We are a leading global software company dedicated to the world of computer aided design, 3D modeling and simulation— helping innovative global manufacturers design better products, faster! With the resources of a large company, and the energy of a software start‑up, we have fun together while creating a world class software portfolio. Our culture encourages creativity, welcomes fresh thinking, and focuses on growth, so our people, our business, and our customers can achieve their full potential.

The Tessent division seeks a highly motivated, creative, and energetic individual as Principal Technology Enablement Engineer, specializing in Design For Test (DFT) and test delivery at chip and system level with their main focus on In‑System Test solutions. Tessent is the market and technology leader of automated tools for insertion of semiconductor Design For Test (DFT) structures, Automatic Test Pattern Generation (ATPG), Embedded Deterministic Test (EDT), Memory Built‑In Self‑Test (MBIST), Logic Built‑In Self‑Test (LBIST), Diagnosis‑Driven Yield Analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test.

This position presents a great opportunity to stay involved technically while getting exposure to marketing and interacting with sales.

As a Principal Technology Enablement Engineer, you are driving the adoption of Tessent In‑System Solutions by the means of strategic and tactical support. You engage with customers at early product definition phase to support architecture and methodology definition that would enable successful adoption while meeting customer requirements. You need to work across multiple stakeholders, namely:
Tessent R&D, field and customers to achieve Technology Enablement targets and roadmaps. This position presents a great opportunity to be involved technically while getting exposure to marketing and interacting with sales.

• Grow adoption and simplify tool usage through ecosystem development
• Strategic support for sales and customers through reviews, flow development, testcases and automation tools
• Work closely with customers to support architecture and methodology definition
• Tactical support for sales and customers through field and internal tickets
• Promote partnerships and differentiation with customers
• Work collaboratively with Tessent R&D and field to test new released products and features within complex IC design flows
• Create and deliver in‑depth technical presentations, develop training material, white papers, contributed articles, and application notes
• Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing
• Work through complex technical issues and independently create solutions and new methodologies
• Present complex principles in simple terms to broad audiences
• Collaborate and share information across team boundaries in written and spoken forms
• Some travel, domestic and international

• BS degree (or equivalent) in Electrical Engineering or related field.
• 6+ years of relevant experience from semiconductor or electronic design automation (EDA) industry
• Expert level knowledge in some of the following areas: DFT for complex ASICs/SoCs, Automatic Test Pattern Generation (ATPG), logic built‑in self‑test (LBIST), embedded memory test, IEEE 1687 IJTAG, hierarchical DFT, chip level integration, DFT architecture, packetized test delivery, IC design flow…