Principal Design Verification Engineer – CPU Subsystem Power Management

## Principal Design Verification Engineer – CPU Subsystem Power Management Apply locations:
Austin, Texas, United States:
Santa Clara, California, United Statestime type:
Full time posted on:
Posted Todayjob requisition :
R-101215##
**** About Si Five
***** As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

With SiFive, the future of RISC-V has no limits.
* At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives;

making the world a better place, one processor at a time. Are you ready?  To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
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* Job Description:

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** About the Role
** SiFive is looking for a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC and subsystem environments, with a strong emphasis on data-center-grade quality, resiliency, and signoff readiness.

This is a principal tech-lead role for an engineer who can define architecture-aware verification strategy early, identify integration and microarchitectural risk, solve difficult subsystem-level problems, and raise the quality bar across the broader power-management verification effort.

The technical scope spans core, cluster, LLC, and uncore power-management behavior, including DVFS, live retention, clock gating, warm reset, power gating, and subsystem interactions across PMC and related control  this role, you will work closely with architecture, RTL, formal, performance, and design verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with strong technical judgment and scalable methodology.  

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** Responsibilities
* ** Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and signoff.
* Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm-reset flows, and multi-domain interactions.
* Drive verification across multiple bench contexts as appropriate, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
* Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity-monitor correctness.
* Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debugability and verification completeness before issues harden late in the program.
* Drive efficient failure analysis and root-cause debug across specification, RTL,…