Principal ASIC Design Verification Engineer

Principal ASIC Design Verification Engineer

Blue Origin is seeking a Principal ASIC Verification Engineer to lead the verification of advanced ASICs for space-based communication systems. This role involves defining verification strategies, establishing methodologies, and ensuring the robustness of high-performance communication hardware. The ideal candidate will have extensive experience in ASIC/SoC verification and a strong background in communication signal processing.

Responsibilities:

• Define end-to-end verification strategy for large space-based communication ASIC or SoC programs.
• Establish verification methodologies, infrastructure, and signoff criteria across block, subsystem, and SoC levels.
• Lead verification planning for complex communication functions such as modem pipelines, FEC engines, digital beamforming, packet processing, and control fabrics.
• Drive alignment among design, architecture, systems, firmware, and validation teams.
• Evaluate verification completeness through coverage, assertions, formal analysis, emulation, and silicon correlation.
• Resolve critical technical issues and direct root-cause analysis for complex functional failures.
• Guide development of reusable VIP, reference models, and regression automation frameworks.
• Mentor technical leaders and enhance the overall verification maturity of the organization.
• Influence future verification roadmap, tool strategy, and reuse models.

Qualifications:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of ASIC/SoC verification experience.
• Expert-level knowledge of System Verilog, UVM, assertions, and verification signoff methodology.
• Proven success leading verification for complex chips or multiple tape-outs.
• Strong understanding of communication signal-processing hardware and system-level integration.
• Excellent technical leadership and cross-organizational communication skills.

Skills:

• Deep expertise in space-based communications, digital modems, phased-array processing, or payload processing.
• Experience with formal property verification, emulation, and performance validation.
• Familiarity with fault tolerance, mission-critical reliability, or radiation-aware verification considerations.
• Experience with architectural modeling and verification planning for hardware/software partitioned systems.
• Strong record of technical innovation and process improvement.