Senior Static Timing Engineer – ASIC Timing & Automation
Listed on 2026-10-14
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Engineering
Systems Engineer, Electronics Engineer, Automation & Mechatronics Engineer, Hardware Engineer
Google is seeking a Senior Static Timing Engineer in Sunnyvale, CA, to lead the physical implementation of high-performance ASICs. You will develop constraints, validate timing, and drive timing closure for large compute chips, collaborating with architecture, logic, and DFT teams.
The role requires hands-on STA expertise, scripting in Tcl/Perl/Python, and evaluating tools and vendors to ensure robust sign-off across complex design flows.
This opening is for the Senior Static Timing Engineer – ASIC Timing & Automation role at Google.
The advertised compensation is 163..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Static Timing Engineer – ASIC Timing & Automation role in the description above.
We appreciate your interest in this position.
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