Senior ASIC​/SoC Physical Design Engineer | P&R & Signoff

TSMC is seeking a Sr. Physical Design Engineer to own the RTL-to-GDS physical implementation flow, including synthesis, floor planning, place-and-route, CTS, STA and signoff from its Austin Design Center, Texas. The role operates on a hybrid schedule with four days in the office.

The successful candidate will lead block-level implementation, perform timing closure and signoff, and work closely with customers at the North Austin site on advanced node flows and EDA tool chains.

This is a strong opportunity to take on the Senior ASIC/SoC Physical Design Engineer | P&R & Signoff role at TSMC
- Taiwan Semiconductor Manufacturing Company Limited.

We invite applications for the Senior ASIC/SoC Physical Design Engineer | P&R & Signoff position located in Town of Texas, WI, United States.

The following opening is for a Senior ASIC/SoC Physical Design Engineer | P&R & Signoff with TSMC
- Taiwan Semiconductor Manufacturing Company Limited.