Senior ASIC DFT Architect – SoC Test & IP Lead
Listed on 2026-10-14
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Engineering
Test Engineer, Hardware Engineer, Systems Engineer
NVIDIA seeks a Senior ASIC Design Engineer to join the DFT team in the US. You will own fuse controller and DFT IP design for leading SoC projects, collaborating with architects and backend teams to ensure cohesive integration.
Responsibilities include developing scalable DFT methodologies, supporting post-silicon bring-up, and mentoring junior engineers. Requires 8+ years in SoC RTL/verification, Verilog, and scripting with Python/Perl/Tcl; UVM is a plus.
Step into the Senior ASIC DFT Architect – SoC Test & IP Lead role at NVIDIA in Town of Montana, WI, United States and grow with us.
This role is for the Senior ASIC DFT Architect – SoC Test & IP Lead role at NVIDIA.
We are seeking a motivated Senior ASIC DFT Architect – SoC Test & IP Lead to join NVIDIA in Town of Montana, WI, United States.
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