Senior Design Verification Architect; SystemVerilog/UVM
Listed on 2026-10-14
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Engineering
Test Engineer, Electronics Engineer, Hardware Engineer
Location: Town of Texas
Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verifying next-generation semiconductor memory interfaces and data buffer silicon. The role centers on defining and executing verification strategy at block and system levels, and owning verification from planning through signoff.
You will architect and maintain System Verilog/UVM test benches, drive coverage closure, and mentor engineers while collaborating with RTL/design teams to ensure
This posting is for the Senior Design Verification Architect (System Verilog/UVM) role at Renesas Electronics Corp., based in Town of Texas, WI, United States.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Town of Texas, WI, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 120..
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