Sr Principal Digital Design Engineer

Locations: San Jose (Holger Way)

Time Type: Full time

Posted On: Posted Today

Job Requisition : R-

Lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications. Drive product execution from concept through RTL development, integration, silicon validation, qualification, and production release. Collaborate across analog, verification, validation, subsystem, SoC, applications, systems, product definition, and customer-facing teams to deliver high-quality mixed-signal solutions.

• Review product requirements, IP architecture specifications, programming models, microarchitecture, interfaces, and implementation plans for automotive and industrial PMIC applications.
• Define and implement digital architectures for mixed-signal PMICs, ensuring alignment with system, performance, quality, reliability, safety, power, and area requirements.
• Lead digital design activities from architecture definition through RTL development, integration, synthesis, timing closure, low-power implementation, silicon bring-up, and production release.
• Design and develop digital control, monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault management functions for PMIC and power conversion products.
• Develop and review RTL, microarchitecture, and design specifications using Verilog/System Verilog and industry-standard design and quality checking tools.
• Drive verification strategy and execution, including test planning, simulation, formal verification, coverage analysis, regression management, and achievement of NXP quality and maturity standards.
• Deliver complete IP solutions, including RTL, verification collateral, supporting documentation, and requirements traceability from specification through implementation.
• Track development metrics including milestones, code and functional coverage, defect resolution, and compliance with design requirements.
• Support silicon debug, characterization, qualification, reliability validation, and production ramp activities.
• Mentor junior engineers and drive continuous improvement in design methodologies, automation flows, and engineering best practices.

• M.S. in Electrical Engineering, Computer Engineering, or a related field required.
• Minimum 10 years of experience in digital IC design and development, including technical leadership and architecture responsibilities.
• Strong understanding of digital design fundamentals, finite state machines, clock-domain crossing, reset architecture, and low‑power design techniques.
• Expertise in RTL design using Verilog/System Verilog for complex digital and mixed‑signal ICs.
• Experience with synthesis, static timing analysis, equivalence checking, DFT, and physical implementation flows.
• Strong knowledge of modern verification methodologies, including UVM, assertions, formal verification, and coverage‑driven verification.
• Experience developing digital controllers for PMICs, power management systems, automotive electronics, or industrial applications is highly desirable.
• Proficiency with industry‑standard EDA tools from Cadence, Synopsys, and Siemens EDA.
• Strong analytical and problem‑solving skills with the ability to develop innovative solutions for complex technical challenges.
• Excellent written and verbal communication skills with proven ability to lead cross‑functional teams in a fast‑paced product development environment.

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