Senior TPU Silicon Design Engineer – ML IP & SoC

Google is seeking a Senior TPU Design Engineer to contribute to ML IPs for Silicon SoCs. You will define microarchitecture details for ML accelerators, specify data flows and integration needs for subsystems, and drive RTL development with rigorous simulations.

You will also ensure schedules, provide customer support, and participate in synthesis, timing/power estimation, and silicon bring-up across Google’s hardware platforms.

Step into the Senior TPU Silicon Design Engineer – ML IP & SoC role at Google in Town of Montana, WI, United States and grow with us.

We invite applications for the Senior TPU Silicon Design Engineer – ML IP & SoC position located in Town of Montana, WI, United States.

The following opportunity is for a Senior TPU Silicon Design Engineer – ML IP & SoC with Google.