TPU SoC Design Engineer: AI Hardware Accelerator
Listed on 2026-10-14
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Google's TPU SoC Design Engineer role in Sunnyvale, CA invites you to shape AI/ML hardware acceleration. You will lead digital RTL design for TPU architecture, developing top-level RTL, architecture, and interconnects for data-center accelerators within a cross-functional team.
The role involves collaboration with Verification, Physical Design, and Firmware teams, focusing on efficient design environments, tool flows, and scalable IP.
For the TPU SoC Design Engineer: AI Hardware Accelerator position at Google, we are reviewing applications now.
We are currently recruiting a TPU SoC Design Engineer: AI Hardware Accelerator for our team in Town of Montana, WI, United States.
This is a great position to take on the TPU SoC Design Engineer: AI Hardware Accelerator role at Google.
As a TPU SoC Design Engineer: AI Hardware Accelerator, you will play an important part at Google in Town of Montana, WI, United States.
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