Analog​/Mixed-Signal Layout Engineer

Analog/Mixed-Signal Layout Engineer Category Chip  Design Location Woburn , MA Experience

More than 6 Years Work Expe.

EducationAD/Professional Qualification

Job Description Media Tek  is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading-edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, Media Tek drives advancements in transformative technologies such as AI, 5G/6G, and Wi-Fi 8.

Our high-performance, power-efficient solutions form the foundation for a smarter, more connected world, enabling devices from smartphones, smart homes, and AI PCs to high-performance computing, automotive, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world-class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.

About the Role We are seeking an exceptional Analog/Mixed-Signal Layout Engineer to develop high‑quality layouts for advanced data converters, power management circuits, and other mixed‑signal IP, from initial planning through final database sign‑off. You will work in a fast‑paced environment, partnering closely with circuit designers to optimize matching, minimize noise coupling and supply drops, and manage parasitics to achieve robust, silicon‑proven designs.

Key Responsibilities:

Develop block‑level and, where applicable, top‑level layouts for ADCs, DACs, bias circuits, LDOs, and other analog/mixed‑signal IP in deep sub‑micron CMOS and FinFET technologies.

Work closely with circuit designers to understand design intent, discuss layout‑related concerns, and co‑create effective solutions.

Apply advanced layout techniques to optimize device matching, reduce noise coupling, minimize supply line drops, and control parasitics.

Support layout implementation in double/multiple patterning processes and ensure compliance with advanced process rules.

Run and interpret EM/IR analysis; implement layout fixes and optimizations based on tool results.

Identify and mitigate layout‑dependent effects (LDE) and fix impacted regions to restore expected performance.

Generate parasitic extractions (e.g., using StarRC, QRC, or similar tools) and collaborate with designers to analyze performance degradation and root causes.

Use Virtuoso L/XL and Calibre to implement layout, run verification, and debug runset violations.

Take ownership of assigned blocks, work independently, and deliver high‑quality layouts on schedule.

Contribute to improving team layout methodologies and best practices.

Main Requirements and Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, with approximately 6+ years of relevant custom layout experience (or equivalent experience).Proven experience laying out ADC, DAC, bias, and LDO circuits in deep sub‑micron CMOS and FinFET technologies.

Experience with double/multiple patterning processes.

Familiarity with EM/IR analysis tools and the ability to interpret results and apply layout fixes.

Strong understanding of layout‑dependent effects (LDE) and practical mitigation strategies.

Solid understanding of traditional analog circuit operation and mixed‑signal design considerations.

Demonstrated ability to innovate and optimize layout solutions for power, performance, and area.

Proficiency with Cadence Virtuoso L/XL layout tools.

Proficiency with Calibre for physical verification and violation analysis.

Experience generating parasitic extractions using StarRC, QRC, or similar tools.

Strong interpersonal, teamwork, and communication skills; able to collaborate…