Lead Physical Design Engineer

All applicants must have the right to work in Switzerland.

Our client is building a world‑class silicon team and is looking for a Lead Physical Design Engineer to take ownership of the complete RTL‑to‑GDSII implementation flow for complex IP and SoC subsystems. This is a hands‑on leadership role where you’ll not only define methodologies and drive execution but also help scale a new backend team around you.

In this position, you’ll define best practices, own PPA and sign‑off quality, and act as the bridge between digital design, custom design, and verification teams. The role combines deep technical involvement with the opportunity to shape the physical design strategy from the ground up.

• End-to-end ownership: Oversee the entire RTL‑to‑GDSII flow — from synthesis and floor planning through place & route, CTS, STA, and sign‑off.
• Methodology & flow: Define, maintain, and automate a robust implementation flow including constraints, UPF/CPF, and sign‑off checks.
• PPA & closure: Drive timing and power closure across multiple corners and modes; lead ECO cycles and ensure strong correlation between synthesis, P&R, and sign‑off.
• Integration: Handle integration of custom macros, SRAMs, and I/O, including clocking strategy, CDC, and hierarchical designs.
• Low‑power design: Own power intent definition and implementation, including isolation, retention, and level‑shifting strategies.
• Team leadership: Build and mentor a backend team (5+ engineers), define ownership areas, and establish repeatable, high‑quality sign‑off standards.
• Automation: Develop reproducible, automated flows using Tcl/Python, CI/CD pipelines, and metrics dashboards for continuous improvement.
• Foundry interface: Collaborate closely with foundry partners on PDK updates, reliability rules, and design sign‑off requirements.

• 5+ full tapeouts owning blocks or subsystems through to sign‑off.
• Deep expertise in one major EDA tool chain (Synopsys or Cadence).
• Proven experience in timing closure, MCMM STA, and hierarchical design integration.
• Strong knowledge of UPF/CPF for multi‑voltage and power‑gated designs.
• Hands‑on experience with grid planning, IR/EM analysis, power optimisation, and ECO implementation.
• Confident in taking technical ownership and guiding others towards sign‑off‑quality results.

Contact:
Tel - ;
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Seniority level:
Mid‑Senior level.

Employment type:

Full‑time. Industries:
Staffing and Recruiting.