Senior Digital IC Designer

Senior Digital Design and Verification Engineer – Zürich, Switzerland

My client is seeking a highly skilled and experienced Senior Digital Design and Verification Engineer to join their innovative team in Zürich, Switzerland. This role offers a unique opportunity to work on cutting‑in‑memory technology, contributing to the design and verification of our digital IP portfolio. The ideal candidate will have a strong background in digital design and verification, with a focus on delivering high‑quality, synthesis‑ready System Verilog RTL and UVM environments.

• Implement RTL for memory‑mapped control blocks, AXI/AHB/APB bridges, FIFOs/scoreboards, arbiters, DMA, and datapaths, ensuring synthesis‑friendly code with a clear reset/CDC strategy.
• Optimise designs for power with a power‑driven mindset and approach.
• Develop UVM test benches, including agents, sequencers, predictors, and scoreboards, driving constrained‑random and directed testing to achieve coverage closure.
• Conduct gate‑level simulations (GLS) with SDF for critical paths and support FPGA prototypes for early hardware/software bring‑up.

• A minimum of 5 years of experience in digital design or verification for ASIC, with strong proficiency in System Verilog RTL and a basic understanding of UVM.

This is an exciting opportunity to work on groundbreaking technology in a collaborative and innovative environment. You will have the chance to make a significant impact on the development of advanced digital IPs while working alongside a team of talented professionals.

Full‑time

Associate