STA Engineer

All applicants must have the right to work in Switzerland

This client building a world-class silicon team and is looking for a Physical Design Engineer with a strong focus on timing closure, synthesis, and sign-off to work on complex IP and SoC subsystems. This is a highly technical, hands-on role where you’ll take ownership of critical backend implementation challenges across advanced ASIC designs.

The position will focus heavily on synthesis, timing-driven implementation, STA, and achieving PPA targets across high-performance designs. You will work closely with digital design, custom design, and verification teams to ensure high-quality implementation and successful tapeout execution.

This is an excellent opportunity to join a growing semiconductor team and contribute to the development of advanced silicon products while helping shape backend methodologies and best practices.

• Strong industry experience within Physical Design / Backend ASIC implementation
• Synthesis
• Static Timing Analysis (STA)
• Timing closure
• MCMM implementation and sign-off
• Strong understanding of timing constraints and timing-driven physical implementation
• Experience across the full RTL-to-GDSII implementation flow
• Strong hands-on experience with Synopsys or Cadence EDA tool chains
• Experience with advanced process nodes and high-performance ASIC designs
• Knowledge of UPF/CPF and low-power implementation methodologies
• Experience with ECO implementation, power optimisation, and sign-off flows
• Understanding of hierarchical design integration and clocking strategies
• Scripting experience with Tcl, Python, or Shell
• Strong debugging and problem-solving skills
• Ability to work effectively within cross-functional engineering teams
• Experience working on CPU, AI accelerator, networking, or complex SoC designs
• Experience with advanced-node implementation and sign-off
• Exposure to low-power and multi-voltage designs
• Previous tapeout experience across complex ASIC products