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Senior Analog IC Layout

Job in Zürich, 8058, Zurich, Kanton Zürich, Switzerland
Listing for: IC Resources
Full Time position
Listed on 2026-05-25
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 CHF Yearly CHF 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Location: Zürich

Senior Analog IC Layout Engineer

My client is seeking a highly skilled and experienced Senior Analog IC Layout Engineer to join their innovative team in Zürich, Switzerland. This role is ideal for a professional with over 5 years of experience in custom analog, SRAM, and custom‑digital layout. This is an exciting opportunity to work on cutting‑edge technologies, including advanced nodes down to 4 nm and below, and contribute to the development of industry‑leading solutions.

Candidate with the legal right to work in Switzerland (Swiss work permit B/C or EEA member state nationals) only can be considered!

Responsibilities
  • Planning and implementing full‑custom layouts for standard cells, custom datapaths, and SRAM periphery/arrays
  • Driving and providing feedback to the design team to achieve the most power‑efficient design layout possible
  • Collaborating with schematic owners to align on constraints, define pins/abstracts, LEF views, keep‑outs, and tiling for memory‑like macros, and coordinate with MBIST/scan wrappers and test hooks
  • Automating and documenting processes by maintaining checklists, templates, and layout guidelines, as well as scripting repetitive tasks using TCL or Python.
  • Ensuring successful tape‑in and silicon of custom blocks or macros with clean DRC/LVS/PEX and correlated post‑silicon parasitics, while delivering comprehensive reports and lessons learned
Qualifications
  • A minimum of 5 years of experience in custom layout for analog, SRAM, or custom‑digital IP
    , with a proven track record of ownership from floorplan to sign‑off
  • Demonstrated expertise in sub‑28 nm nodes
    , including practical knowledge of FinFET/FDSOI, multi‑patterning/EUV constraints, and coloring
  • Proficiency in analog layout techniques such as common‑centroid, interdigitation, current‑mirror symmetry, matched routing, shielding/guard rings, and substrate noise isolation
  • A solid understanding of timing, IR, and EM implications of layout, with the ability to read extraction/timing reports and collaborate with designers, PD, and STA teams
  • Strong communication skills, rigorous documentation practices, and a collaborative mindset to work effectively across custom design, digital, and backend teams
Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Staffing and Recruiting

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Position Requirements
10+ Years work experience
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