Lead Custom Logic Design Manager

Our client is a fast-growing, venture-backed startup redefining the boundaries of computing. The patent-pending Compute-in-Memory (CIM) technology seamlessly integrates into existing chip designs, boosting performance and energy efficiency for AI and IoT applications by orders of magnitude.

Direct a team of Custom Design, Layout, and Physical Design engineers in implementing a near-memory compute product, consisting of bulk memory, register files, and custom and synthesized digital logic, in a leading edge (across the whole design cycle.

You will be responsible for guiding the team from the internal architectural definition, through exploration of designs, implementation, verification, and sign off. The ideal profile is of someone who works independently, is self-motivated, and has a well-structured approach to problem-solving, with the ability to communicate effectively within cross-functional teams.

• Own the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and CxR-adjacent custom blocks.
• Design verify memory or datapath subsystems, including data drivers, multipliers, adders, register files, timing/control FSMs, etc..
• Engineer for advanced nodes: close on variation (corners, Monte-Carlo), stability, noise/IR drop, device reliability, and wake-up/low-power behaviors in FinFET and FDSOI.
• Integrate for product: define clean digital boundaries (standard-cell and bus interfaces), latency/ handshake contracts, and timing budgets.
• Silicon correlation: plan bring-up, build characterization benches, analyze ATE data, and publish correlation and errata with clear fixes.
• Redundancy test: specify and validate redundancy/repair schemes; work with DFT (MBIST and Scan) test coverage; sign off on a production test plan.
• Partner with layout: co-plan floor plans, matching/guarding, shielding, and routing topologies; review extraction and fix EM/IR issues early.
• Elevate method team: coach designers, run reviews, enforce checklists, and grow automation (Python/Tcl) for regressions, reporting, and collateral generation.
• Tape-in and silicon of at least one production-grade CxR custom memory block meeting spec across PVT, with signed correlation and test reports.
• A reusable design kit (models, constraints, verification plans, char scripts, checklists) that shortens the following variant’s cycle time.
• A high-functioning custom team with clear ownership (periphery, timing/control, modeling, characterization) and reliable delivery metrics.
• Quantified PPA and yield gains from design or methodology improvements you led.

• Tape-in and silicon of at least one production-grade CxR custom memory block meeting spec across PVT, with signed correlation and test reports.
• A reusable design kit (models, constraints, verification plans, char scripts, checklists) that shortens the following variant’s cycle time.
• A high-functioning custom team with clear ownership (periphery, timing/control, modeling, characterization) and reliable delivery metrics.
• Quantified PPA and yield gains from design or methodology improvements you led.

• MS or PhD in Electrical/Computer Engineering (or similar) and 10+ years in custom digital or memory design.
• Track record of end-to-end ownership of production-grade functional blocks, including sign-off.
• Deep understanding of high-performance and low-power circuit design on FinFET nodes (stability, variation, leakage, performance).
• Knowledge of device physics, including transistor and non fet devices, capacitive and power tradeoffs, functionality of digital logic circuits.
• Experience leading a small team (mentoring, reviews, planning) and coordinating tightly with layout, digital, backend, DFT, and test.
• Clear communication, structured documentation, and a quality-first mindset.
• Can work independently, is self-motivated, and has a well-structured approach to problem-solving, with the ability to communicate effectively within cross-functional teams.

• Scripting for design and characterization automation (Python, Tcl) and model/report generation.
• DTCO/STCO exposure to align product goals.
• Familiarity with compute-in-memory constraints and with integrating custom memory into large digital systems