Physical Design Engineer

An innovative semiconductor company expands its silicon engineering team and hires a Physical Design Engineer to play a key role in developing next-generation ASIC and SoC products.

This position offers the opportunity to work across the complete implementation flow, taking designs from RTL through to signoff while collaborating closely with front‑end, verification and system teams. You’ll be involved in solving complex timing and physical implementation challenges on advanced technology nodes and will have genuine influence over design methodologies and flow improvements.

• Driving ASIC implementation from synthesis through place & route, timing closure and final signoff.
• Developing and refining timing, power and physical constraints to achieve demanding performance targets.
• Performing static timing analysis and resolving complex implementation challenges.
• Working closely with RTL and verification teams to ensure designs are optimised for physical implementation.
• Supporting low‑power implementation strategies and modern SoC integration activities.
• Enhancing automation and methodology through scripting and flow development.
• Contributing to successful tapeouts and post‑implementation analysis.

• Proven experience in ASIC Physical Design and back‑end implementation.
• Strong understanding of synthesis, place & route, clock tree synthesis, STA and timing closure.
• Experience owning or contributing to the RTL‑to‑GDSII flow.
• Knowledge of modern SoC architectures and integration flows.
• Familiarity with Verilog/System Verilog and an understanding of the interaction between RTL and physical implementation.
• Hands‑on experience with industry‑standard EDA tools such as Synopsys, Cadence or Siemens tool suites.
• Scripting experience using Python, Tcl or similar languages to improve design productivity and automation.
• Ability to debug and solve complex implementation and timing issues.