Standard Custom Design Engineer

Own critical mixed-signal subsystems that bring our compute-in-memory SRAM (Compute RAM) from design to silicon and into production. You will design, verify, and characterize custom blocks, including full-custom digital datapaths and memories, and collaborate tightly with our digital and layout teams to hit aggressive PPA and quality targets on modern CMOS nodes, down to 4nm and below. You will deal with multi-disciplinary topics ranging from traditional mixed-signal design to solving digital timing constraints.

• Develop AI-related building blocks as part of our in-memory computing technology.
• Partner across disciplines on interfaces, buses/standard-cell boundaries, and timing/power budgets.
• Contribute to IP-quality specifications, reviews, reusable verification collateral, and documentation ready for internal reuse and customer delivery.
• Continuously improve flows through scripting/automation (e.g., Python/Tcl) for characterization, report generation, and regressions, guaranteeing reproducibility and reliability.

• Complete and document one or more IP blocks
• Tape-in and silicon of at least one sub-system meeting spec across PVT; complete post-production test plan and correlation report signed off.

• Quality-oriented approach
• Proven design ownership in one or more of: datapath/standard cells design, memory/SRAM design, data-converters, ultra-low-power amps, power-management, references, PLLs, sensor signal processing chains.
• Clear technical communication; structured planning; comfort working cross-functionally with digital/custom/layout.

• Exposure to datapath/arith/bus/standard-cell co-design boundaries (device-level parasitics, signal-integrity hand-offs, and glitch reduction).
• Scripting for automation (Python/Tcl) in mixed-signal flows
• Familiarity with compute-in-memory or memory-periphery constraints (matching, IR/EM, variation, testability)