Senior Physical Design Engineer

Own timing closure and sign-off for complex IP and SoC blocks that integrate our full-custom ComputeRAM® macros. You will drive Static Timing Analysis across corners and modes, shape clean constraints, partner closely with synthesis, place-and-route, and clock-tree teams, and lead ECO loops to convergence. Your work ensures robust clocks, predictable closure, and high-quality sign-off on modern nodes. You will work closely with our full-custom team to integrate our custom IPs into the traditional digital backend flow.

• Build, refine, and maintain timing constraints for blocks and top-level designs, including clocks, generated clocks, I/O timing, and exceptions.
• Run STA across all relevant corners and modes, close setup and hold, and manage variation and correlation from synthesis to P&R to sign-off.
• Guide clock-tree strategy and debugging with clear targets for skew, jitter, and latency; collaborate with P&R on placement, buffering, and routing choices that affect timing.
• Lead timing and functional ECOs, track impacts, and land repeatable closure with minimal overhead.
• Support gate-level verification needs with timing data, and ensure timing/constraints remain consistent with sign-off views.
• Automate timing checks, report generation, and regressions using scripting, and contribute checklists and documentation that others can reuse.

• Clean timing closure at block and top level across all defined corners and modes, with stable constraints and traceable waivers.
• Documented timing methodology adopted by the team, with measurable reductions in ECO cycles and predictable time-to-close.
• Correlated results between synthesis, P&R, and sign-off, demonstrated by repeatable reports and post-route margins on critical paths.

• 5+ years in ASIC physical design with a strong emphasis on timing closure and sign-off.
• Familiarity with STA tools and flows, including clocking, cross-domain concerns, multi-clock designs, and hierarchical closure.
• Hands-on experience working with synthesis and place-and-route to drive timing-aware decisions and guide ECOs to closure.
• Scripting ability to automate timing analysis and reporting.
• A collaborative approach with front-end, backend, and verification teams.

• Experience with power-aware and low-power backend.
• Background in scan and test timing, and awareness of verification and physical verification interactions with timing.
• Exposure to advanced nodes and hierarchical sign-off on large designs.
• Context working on accelerators or memory-adjacent designs where timing and integration are tightly coupled.