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Principal Analog IC Layout Engineer

Job in Zürich, 8081, Zurich, Kanton Zürich, Switzerland
Listing for: IC Resources
Full Time position
Listed on 2026-09-12
Job specializations:
  • Engineering
    Electronics Engineer, Hardware Engineer, Electrical Engineering, Systems Engineer
Salary/Wage Range or Industry Benchmark: 85000 - 113000 CHF Yearly CHF 85000.00 113000.00 YEAR
Job Description & How to Apply Below
Location: Zürich

I am recruiting for a Principal Analog/RF IC Layout Engineer to join my client's team in France. I am looking for an experienced IC layout professional with strong custom analog and mixed-signal experience. The Principal Analog/RF IC Layout Engineer will work closely with circuit designers on the layout and verification of complex analog and mixed-signal IP, taking responsibility from floor planning through to chip-level integration and final verification.

Responsibilities
  • Lead custom analog and mixed signal IC layout from floor planning through to final integration
  • Manage chip level integration of analog, mixed signal and ASIC blocks
  • Complete block level and top level verification, including DRC, LVS, ERC, extraction and DFM
  • Work with designers on floor planning, matching, parasitic management and critical signal paths
  • Coordinate layout activities and schedules with other layout engineers
  • Review power and ground routing, electromigration, signal coupling and other layout related risks
  • Support final chip finishing and ensure layouts meet performance and manufacturing requirements
Requirements
  • Around 8 to 10 years of analog, mixed-signal, or RF IC layout experience
  • Strong understanding of high speed layout and parasitic effects across different process technologies
  • Experience with Cadence Virtuoso
  • Strong ability to interpret Calibre DRC, ERC and LVS results
  • Good understanding of IR drop, RC delay, electromigration and chip finishing
  • Experience with floor planning and area estimation
  • Strong communication skills and the ability to work closely with circuit designers
  • FinFET experience is beneficial but not essential
  • High-speed BiCMOS layout experience would be advantageous

The role can be based anywhere in France, but candidates must already have the right to work in France, as no sponsorship is available.

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