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Principal Engineer Digital Design; f​/m​/div

Job in Zürich, 8081, Zurich, Kanton Zürich, Switzerland
Listing for: Infineon Technologies AG
Full Time position
Listed on 2026-10-07
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Electrical Engineering, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 190000 CHF Yearly CHF 140000.00 190000.00 YEAR
Job Description & How to Apply Below
Position: Principal Engineer Digital Design (f/m/div)
Location: Zürich

Principal Engineer Digital Design – Research & Development

#We Are In  for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Principal Engineer Digital Design in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?

Your Role

Key responsibilities in your new role

  • Conceptualize and translate custom complex signal processing algorithms from MATLAB to RTL
  • Evaluate performance trade-offs and propose innovative improvements to existing UWB features
  • Perform simulations, synthesis, timing and power analysis
  • Collaborate closely with cross-functional teams including verification, system, analog, and application engineering with internal and external stakeholders
  • Document and share specifications and architectural choices
  • Contribute to silicon validation, ensure production release, and drive continuous improvement of existing IPs and design flows
  • Mentor and support team members on a day-to-day basis
Your Profile

Qualifications and skills to help you succeed

You are a proactive problem-solver with strong initiative and a passion for interdisciplinary collaboration. You approach challenges with curiosity and flexibility, take full responsibility for your work, and thrive as an autonomous team player.

  • Master's or PhD degree in Electrical Engineering, Computer Science, or in a related field
  • At least 5 years of professional or academic experience in ASIC RTL to GDS flow with ability to understand and debug VHDL and write System Verilog RTL
  • Experience in custom digital signal processing design at hardware level, ideally for wireless communications
  • Experience in RF and wireless communication technologies is a plus
  • Experience in UWB communication protocol is a strong plus
  • Tape‑out experience in advanced technology nodes with knowledge of UPF flow, synthesis, timing analysis, place-and-route, DFT and CDC implementations is a plus
  • Fluency in English (mandatory)

Please send us your CV in English.

Equal Employment Opportunity

We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting. Please let your recruiter know if they need to pay special attention to something to enable your participation in the interview process. We base our recruiting decisions on the applicant’s experience and skills. We welcome applicants from all backgrounds.

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