Senior Digital Design Engineer SoC and AI; f​/m​/d

Renesas IC Design Power Division in Zurich develops advanced analog and mixed-signal integrated circuits for power-management and wireless-power applications, delivering complex semiconductor products from architecture and design through silicon validation and volume production.

Renesas IC Design Power Division in Zurich develops advanced analog and mixed-signal integrated circuits for power-management and wireless-power applications, delivering complex semiconductor products from architecture and design through silicon validation and volume production.

The successful candidate will combine SoC digital design with dedicated technical ownership of internal AI-assisted engineering tools supporting requirements management and specification development. The role includes ongoing software development and maintenance, close collaboration with engineering users, and integration of AI/LLM capabilities into the design flow. Prior experience integrating AI into IC design workflows is an essential requirement for this position.

• Take technical ownership of internal engineering tools and their existing codebases. Develop enhancements, resolve defects, maintain documentation, manage releases, and provide ongoing support to the engineering team.
• Develop and validate AI-assisted workflows that translate product requirements into specifications for each engineering discipline. Work with domain experts to preserve traceability to source requirements and manage dependencies and requirement changes.
• Build automated tests and review workflows to assess the completeness, consistency, and correctness of generated specifications. Ensure outputs can be checked and approved by the responsible engineers.
• Translate user feedback into tool improvements, maintain integrations with engineering workflows, and evaluate additional AI/LLM applications for requirements analysis, documentation, RTL development, and verification.
• Translate system and product requirements into digital specifications and micro-architectures. Develop RTL in Verilog/System Verilog and integrate embedded processors, memories, peripherals, register maps, and on-chip buses into mixed-signal SoCs.
• Own digital design activities including lint, CDC/RDC analysis, synthesis, static timing analysis, and low‑power design. Support physical implementation and timing closure.
• Collaborate with system, analog, verification, firmware, and physical design teams on SoC integration, clock and reset architectures, mixed-signal interfaces, design reviews, and verification planning.
• Support silicon bring-up, laboratory debugging, and product validation through the transition to volume production

• Proven hands‑on experience developing and integrating AI‑based tools into IC design workflows is required. Candidates must be able to demonstrate implemented solutions in areas such as requirements engineering, specification generation, RTL design, verification, or design‑flow automation.
• MSc or PhD in Electrical Engineering, Microelectronics, Computer Engineering, or a related field.
• Typically 5+ years of relevant experience in digital IC/SoC design, with experience taking designs from specification through successful silicon.
• Strong practical experience with Verilog/System Verilog, RTL design, and digital subsystem integration.
• Solid understanding of SoC architectures, including embedded processors, memories, peripherals, register architectures, and on‑chip buses such as AMBA AHB/APB.
• Experience with lint, CDC/RDC, synthesis, static timing analysis, and timing closure, together with an understanding of clock/reset architectures and low‑power design techniques.
• Practical software‑development…