Doctoral​/Postdoctoral Position in Low-Jitter Clock Generation Single-Photon RGB-D Image Sensors

The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at the Department of Information Technology and Electrical Engineering (D-ITET), ETH Zurich, invites applications for a doctoral or postdoctoral position in the area of low-jitter frequency synthesis and clock generation. The position is part of an international industry‑academia research project developing a next‑generation single‑chip RGB‑D image sensor for robotics.

Robots in manufacturing need to see colour and depth at the same time, reliably, both indoors and in bright sunlight. Today this usually takes several separate sensors. The project develops a monolithic RGB‑D sensor System‑on‑Chip that combines colour imaging with direct time‑of‑flight (dToF) depth sensing on a single‑photon avalanche diode (SPAD) array.

In a dToF sensor, depth is measured from the arrival time of photons. The precision of the clock driving large arrays of parallel time‑to‑digital converters directly limits depth accuracy. Timing errors of a few picoseconds already turn into visible depth errors. Within the project, our group is responsible for the core analog building blocks of the sensor chip. This position focuses on the on‑chip clock generator: a phase‑locked loop (PLL) operating at ultra‑low jitter at very low power consumption, together with clock synchronization across the sensor array.

• Develop the architecture and system‑level specification of a low‑jitter, low‑power PLL in close exchange with the industrial chip design partner
• Investigate new techniques for low‑jitter, energy‑efficient frequency synthesis and clock distribution for large arrays of time‑to‑digital converters
• Design, layout and tape out the circuits in advanced CMOS technology, and characterize the chips in our measurement lab
• Refine the design based on measurement results and support its integration into the sensor SoC
• Publish your results at leading venues of the field and present them at international conferences
• Contribute to the teaching activities of the group

• Master's or Ph.D degree in electrical engineering or a closely related field, with excellent grades
• Solid background in analog and mixed‑signal integrated circuit design. Experience with PLLs, oscillators, clock generation or data converters is a strong advantage
• Hands‑on experience with Cadence Virtuoso or similar tools
• Previous tape‑out or lab measurement experience is a plus
• Strong analytical skills and enthusiasm for pushing circuit performance to its limits
• Ability to work independently and in an international team that spans academia and industry
• Excellent written and spoken English

The Energy‑Efficient Circuits and Intelligent Systems Group (EECIS) focuses on circuits and systems for next‑generation computing platforms. Its main interest is the energy‑efficient design of the key circuit blocks of miniaturized systems, including analog interfaces, optical and RF transceivers, frequency synthesizers, power management units and data converters.

You can look forward to:

• A research project with a clear path from idea to silicon to a real robotic application
• Close collaboration with industrial partners and with the robotics research at ETH Zurich
• A complete IC design and verification environment
• Tape‑out support from the ETH Microelectronics Design Center, with access to advanced CMOS processes through multi‑project wafer runs
• Our own measurement lab equipped with advanced instruments, plus the low‑noise measurement labs at the Binnig and Rohrer Nanotechnology Center
• A diverse, international and highly motivated team, with collaborations across ETH and worldwide
• A group with a strong record in low‑jitter frequency synthesis

Working, teaching and research at ETH Zurich