Senior Analog Design Engineer Augora Hills, CA

Opportunity Overview

Teradyne’s Semiconductor Test Division in Agoura Hills, CA seeks a Senior Analog Design Engineer to design low‑ and high‑speed circuits in mixed‑signal ICs for Automatic Test Equipment (ATE) instruments, focusing on FINFET, general CMOS, and BCD technologies.

• Develop detailed circuit specifications for mixed‑signal circuits.
• Conceive circuit architectures and transistor‑level topologies that meet performance requirements.
• Implement physical layouts of high‑speed circuits or assist in layout efforts.
• Optimize circuits via simulation using Cadence EDA tools across all process and operating conditions.
• Integrate circuit elements into large analog/mixed‑signal ASICs.
• Participate in the characterization of ASIC circuits.

• MSEE with 5 years of experience or PhD in electrical engineering with 3 years of experience in high‑frequency, high‑integration mixed‑signal IC design.
• Thorough knowledge of high‑frequency, broadband analog mixed‑signal IC design, both electrical and physical.
• Experience designing VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high‑frequency I/Os, high‑frequency CML designs, high voltage, and power circuits.
• Solid understanding of CMOS semiconductor device physics, device modeling, electromagnetic theory, transmission line theory, thermal effects of circuit topologies, and package types.
• Involvement in all phases of multiple IC developments from specification to product introduction.
• Proficiency in Verilog or Verilog‑A modeling.
• Experience with Cadence SKILL or Ocean scripting for automating test benches.
• Generic experience in deep sub‑micron CMOS (