SoC Logic Design Engineer

Job Details

Job Description:

Join Intel's distinguished team as an SoC Logic Design Engineer. In this role, you will pioneer the development of cutting‑edge System‑on‑Chip (SoC) solutions, contributing to Intel's mission of creating transformative technology that drives global innovation. As a key member of our team, you will have the opportunity to influence the architecture, design, and integration of next‑generation SoCs. Your contributions will directly impact Intel's ability to deliver world‑class products with optimal performance, power efficiency, and scalability, shaping the future of the semiconductor industry.

• Develop high‑quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs.
• Collaborate with architects to define and implement microarchitecture features of SoC blocks.
• Integrate and validate Intellectual Property (IP) blocks and subsystems into full‑chip SoC designs.
• Perform quality checks and optimize designs to meet power, performance, area, and timing objectives, ensuring seamless production readiness.
• Review verification plans to confirm design features are thoroughly verified and address any RTL test failures with corrective measures.
• Employ secure development practices to mitigate security risks and maintain design integrity.
• Work with IP providers to integrate and validate IPs at the SoC level.
• Drive quality assurance compliance to enable efficient IP‑SoC handoffs.

To excel in this role, you must meet the following requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of relevant experience.
• Master's degree in Electrical Engineering, Computer Engineering, or a related field and 3+ years of relevant experience.
• PhD in Electrical Engineering, Computer Engineering, or a related field and 6+ months of experience.

• Expertise in RTL development, System Verilog, and SoC logic integration.
• Proficiency in microarchitecture definition, logic design, and simulation.
• Strong understanding of SoC design methodologies, including timing/power convergence and physical implementation.

Candidates with the following qualifications will have an advantage:

• Hands‑on experience with Python, Perl, or other scripting languages.
• Familiarity with advanced Front‑End RTL Design tools such as Lint, CDC, Synthesis, and Static Timing Analysis (STA).
• Experience in validation development, pre‑silicon testing, and DFT/DFD tools.
• Knowledge of industry‑standard IPs, fabrics, and UVM‑based verification.

We are looking for innovators passionate about advancing technology. Embark on a career journey where your work will leave a profound impact on the future of computing. Apply now and help Intel create world‑changing technology.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary

Location:

US, Oregon, Hillsboro

Additional Locations: US, California, Santa Clara, US, Texas, Austin

Business group:
The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit…