Principal Mixed Signal Design Verification Engineer

Qorvo’s fast-growing Power Management division, focused on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IoT and Industrial applications, is looking for an experienced Top-level Design Verification Engineer to create next generation and world-class designs in power management solutions.

• Serve as customer-facing for catalog and custom power‑management ICs including motor driver, power‑loss protection, point of load, and battery management IC solutions.
• Develop and execute metric‑driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use‑case.
• Develop constrained random tests and automated checkers within our TLDV UVM environment.
• Build high performance, accurate RNM or VerilogAMS models to support TL simulation.
• Collaborate with design team to resolve issues identified during verification.
• Partner with internal design and test teams to ensure device first‑pass testability.
• Continuously improve and align verification methodologies with industry best practices. Automate verification tasks where applicable.

• Advanced degree in Electrical Engineering or a related field, with strong focus on mixed‑signal circuit design and verification.
• 12+ years of experience in AMS design or verification of analog and power‑management ICs.
• Proficiency in UVM environments, including test cases, coverage models, and global checkers.
• In‑depth knowledge of power‑management building blocks such as LDO, Amplifiers, Bandgaps, DCDC regulators, Oscillators, and asynchronous state machines.
• Excellent problem‑solving and debugging skills. Effective communication and collaboration skills.
• Expertise in mixed‑signal concepts such as Spice/Spectre and event‑based simulator, co‑simulation environment, simulation debug, silicon debug.

• Experience in Top‑Down Design Methodology.
• Proficiency in shell or Python scripting.
• Familiarity with SV‑UDN/EENET modeling techniques.
• Experience with both GUI and command‑line simulation flows.
• Proficiency with SV Assertions and Functional coverage.
• Understanding integration of AI into a verification workflow.

Other: 10% or less domestic or international travel may be required

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.