DFT design​/methodology development Engineer

Overview

Location:

Albany (NY) — preferred, Santa Clara (CA), or Tokyo (Japan).

• You will be responsible for the Design for Test (DFT) strategy within the 2nm reference flow. This role involves integrating advanced Scan and MBIST tools to ensure high testability for complex GAA designs. You will also lead the evaluation and adoption of next-generation DFT methodologies to address the challenges of ultra-fine process nodes.
• Integrate Scan and MBIST (Memory Built-In Self-Test) tools into the digital reference flow.
• Evaluate and implement advanced DFT technologies, such as Streaming Scan Network (SSN), to optimize test data volume and test time.
• Develop and validate ATPG (Automatic Test Pattern Generation) methodologies utilizing cell-aware (intra-cell) fault models to achieve high defect coverage at the 2nm node.
• Conduct evaluation and feasibility studies for new failure analysis methodologies to improve yield ramp-up.
• Work closely with EDA vendors to implement these advanced DFT features and collaborate with design partners for pattern generation and silicon-based failure diagnosis.
• Support DFT implementation and pattern execution for internal Rapidus test chips.
• Provide customers with comprehensive DFT guidelines and technical support.

• Solid understanding of DFT methodologies (Scan, MBIST, ATPG).
• Experience with advanced process nodes (7nm FinFET and beyond) is preferred but not mandatory.
• Familiarity with advanced DFT architectures (e.g., SSN, packetized test) and cell-aware testing is highly desirable.
• Proven ability to collaborate with external stakeholders, including EDA vendors and design service partners.
• Collaboration:
  
  Proven ability to work effectively with external stakeholders, including EDA vendors and design service partners.
• Education:
  
  BS/MS/PhD in Electrical Engineering or a related technical field.
• Language:
  Professional proficiency in English (Japanese skills are a plus).