Distinguished Engineer, ASIC;

About Butterfly Network

Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with proprietary Ultrasound‑on‑Chip semiconductor technology and cloud software. We commercialize the world’s first single‑probe, whole‑body portable ultrasound device and continue to develop AI‑powered solutions that make imaging affordable and accessible.

Distinguished Engineer, Digital ASIC Designer at Butterfly Network, Inc. (NYSE: BFLY) will lead the design, implementation, and verification of digital signal processing, high‑speed interfaces, and system‑on‑chip logic for next‑generation ultrasound imaging products.

• BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience.
• 8–12+ years of digital IC/ASIC/SoC design experience with hands‑on RTL ownership.
• Strong understanding of digital IC implementation at the silicon level, including timing closure, clock/reset domain architecture, power‑aware design, and PPA tradeoffs.
• Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design.
• Strong RTL skills in System Verilog/Verilog to implement silicon‑proven digital architectures, including pipelined datapaths, control logic, state machines, and high‑throughput streaming interfaces.
• Experience architecting sustained high‑throughput digital datapaths, including buffering, arbitration, back pressure, bandwidth budgeting, and SRAM/memory hierarchy design.
• Prior work at advanced technology nodes (28 nm or smaller), including timing closure challenges and integration of third‑party IP.
• Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff.
• Comfortable working cross‑functionally with analog, systems, and packaging/board teams to close chip‑level requirements and integration details, including hardware‑firmware interfaces (register maps, control/status paths, data‑plane contracts).

• Experience implementing compute‑intensive digital pipelines (DSP, beamforming, AI, or MAC‑heavy/vector datapaths).
• Exposure to medical imaging/ultrasound systems, beamforming pipelines, or sensor data acquisition architectures.
• Experience designing or integrating programmable digital compute blocks (AI accelerators, MPUs, eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs.

Hybrid model with two or more days a week in the office. Potential U.S. office locations include:

• San Francisco Bay Area
• Burlington, MA

Butterfly Network Inc. is an equal opportunity employer and a participant in E‑Verify. We do not accept agency resumes for this position. All candidates must be legally authorized to work in the United States and must not require sponsorship. This role requires adherence to all company security policies, completion of required security awareness training, and safeguarding company data and systems.