ASIC​/FPGA Design and Verification Engineer

Job Description

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth.

We are looking for ASIC/FPGA Design or Verification Engineers (Lead, Senior, or Principal) to join the Boeing Electronic Products team in Albuquerque, NM. This team focuses on ACs and FPGAs for a range of Boeing products, from satellite phased array systems to aircraft computing and networking equipment.

• Lead FPGA/ASIC designs and manage multi‑FPGA/ASIC programs and teams.
• Collaborate with customers, system engineers and hardware engineers to capture requirements and architect digital logic.
• Explore trade‑space of potential ASIC/FPGA technologies, evaluating Schedule, Cost, Risk, Area, Power (SCRAP) and performance.
• Implement designs using current industry practices, from block‑level micro‑architecture through HDL coding and physical design.
• Integrate DSP IP and third‑party IP as needed.
• Perform static timing analysis, physical verification checks and functional coverage.
• Develop self‑checking, reusable test benches with UVM and object‑oriented concepts.
• Drive prototyping, validation and hardware integration testing with specialized test equipment.
• Train, mentor, and build effective project teams.

• Conduct unit‑level testing, verification, and validation of embedded software and firmware.
• Create and maintain technical documentation: requirements, design specifications, test plans, and interface control documents.
• Support integration from hardware bring‑up to final system validation.
• Analyze and enhance resource efficiency, stability, scalability and performance within low‑power/memory constraints.

• Bachelor of Science in Engineering, Computer Science, Data Science, Mathematics, Physics, Chemistry or an equivalent degree related to the work statement.
• 9+ years of ASIC/FPGA design or verification experience, or a Master’s degree and 7+ years of experience.
• Experience with ASIC/FPGA architectural definition, detailed design implementation, and functional verification in System Verilog.
• Professional hardware‑based integration and testing of ASIC/FPGA designs.

• Level 5 (Senior): 14+ years of related experience.
• Level 6 (Principal): 20+ years of related experience.
• Master’s degree in EE or related field.
• Leadership of design/verification teams with progress reporting.
• Hardware emulator experience, especially Palladium.
• Proficiency in System Verilog, System Verilog Assertions, UVM, Object‑oriented concepts.
• Experience with functional coverage models, code coverage closure, high‑speed Ser Des interfaces.
• Proficiency in scripting (Make, Perl, Python), revision control (svn, cvs, git), Linux environment proficiency.
• Knowledge of space‑based design techniques and radiation mitigation.
• Demonstrated history of first‑pass success with ASIC designs.

This position requires the ability to obtain a U.S. Security Clearance and U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post‑Start is required.

Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, disability, or protected characteristics.

• Salary ranges:
  Lead (Level
  4) $136,850 – 185,150;
  Senior (Level
  5) $164,900 – 223,100;
  Principal (Level
  6) $197,200 – 266,800.
• Relocation assistance for eligible internal candidates.
• Competitive base pay and variable compensation opportunities.
• Standard benefits including medical, dental, vision, flexible spending accounts, health savings accounts, retirement plans, life and disability insurance, paid leave, and unpaid time away options.

1st shift.

Employer will not sponsor employment visas.

This U.S. based position requires U.S. Person status per U.S. export control regulations.

Successful candidates must satisfy the Company’s Conflict of Interest (COI) assessment process.