Analog Design Manager; Power & Clock IP

Job Description

onsemi (Nasdaq: ON) is a global leader in intelligent power and sensing technologies, driving innovation to build a safer, cleaner, and smarter world. With a strong focus on automotive, industrial, and AI data center markets, we are shaping the future of vehicle electrification, sustainable energy, and advanced automation.

About the Treo Platform

The newly launched Treo Platform is a cutting-edge analog and mixed-signal solution built on 65nm Bipolar-CMOS-DMOS (BCD) technology. Supporting voltage ranges from 1–90V and operating temperatures up to 175°C, Treo is engineered for high-performance applications in automotive, medical, industrial, and AI data centers. Its modular architecture simplifies design, reduces system costs, and accelerates time-to-market. All products are manufactured at our state-of-the-art 300mm fab in East Fishkill, NY.

About the Role

We’re seeking an experienced Analog Design Team Manager to lead the development of power and clock analog IP blocks for platform-based SoC products on the Treo platform at onsemi
. This role combines technical depth with strong people leadership: you’ll set IP strategy, define best-in-class design flows, drive IP delivery to product integration teams to enable execution to tape-out, and nurture a high-performing team. If you’re excited about how AI will transform analog design, you’ll have an opportunity to explore and pilot data-driven methods and tooling to elevate our design quality and velocity.

Key Responsibilities

• Lead, mentor, and grow a team of 10–20 analog designers and layout engineers; set goals, conduct performance reviews, and build succession plans.
• Foster a culture of accountability, excellence, and collaboration, emphasizing design quality, schedule integrity, and cross-functional communication.
• Technical Ownership (Power & Clock IP)
  • Own architecture, design, verification, and delivery of power management (LDOs, DC/DC, charge pumps) and clocking (PLLs, DLLs, oscillators, clock distribution) blocks for Treo-based SoC platforms.
  • Define IP specifications, corner cases, and sign-off criteria; drive first-time-right silicon through rigorous pre-silicon analysis and post-silicon correlation.
  • Deliver analog blocks into a digital on top subsystem ready for product integration
• Execution & Program Management
  • Plan and manage project schedules, resources, and risk mitigation across multiple concurrent IPs; ensure milestones (spec, RTL/AMS integration, layout, tape-out) are met.
  • Collaborate closely with digital design, verification, PDK/technology, validation/test, Functional Safety and product/operations teams to enable smooth platform integration.
• Tools, Flows & Quality
  • Champion state-of-the-art analog simulators, tools, and flows (e.g., schematic capture, SPICE/AMS simulators, Monte Carlo/statistical analysis, electromigration/IR checks, reliability).
  • Establish and maintain design methodologies, checklists, and data-driven dashboards for systematic reviews and sign-off.
• Explore how AI/ML can augment analog workflows (e.g., design space exploration, model-order reduction, layout-aware optimization, testbench generation, corner selection, bug triage).
• Pilot and evaluate emerging solutions in partnership with EDA vendors and internal CAD/Methodology teams; define measurable outcomes for adoption.
• Support lab bring-up and silicon characterization; partner with validation to root-cause issues and drive corrective actions.
• Contribute to platform reuse strategy and documentation to accelerate future programs and improve customer experience.

Minimum Qualifications

• 10+ years of experience in analog IC design, with 5+ years in a management/leadership role.
• Proven track record architecting and designing power management and clocking analog IP for platform-based SoCs.
• Proficiency with modern analog simulators, tools, and flows (e.g., SPICE/AMS, Monte Carlo, corners/variability, noise/jitter analysis, reliability/EM/IR, RC extraction, mixed-signal co-sim).
• Solid understanding of device physics, analog architectures, layout-dependent effects, and process/PDK interactions across corners and aging.
• Experience leading…