Senior Physical Design Engineer

We are seeking an experienced Senior Physical Design Engineer with deep expertise in advanced node technologies and 3D Integrated Circuit (3

DIC) / 2.5D Integrated Circuit (2.5

DIC) design methodologies. The ideal candidate will have 8-12+ years of hands‑on experience in physical design, with a proven track record in full‑chip integration, timing closure, and working on cutting‑edge process nodes (7nm and below).

• 8-12+ years of hands‑on experience in Physical Design for semiconductor chip development.
• Leverage hands‑on experience with 7nm or below process nodes (5nm/3nm preferred) to optimize complex designs
• Strong background in full‑chip integration and timing closure for complex SoC/ASIC designs
• Enable 3
  
  DIC and 2.5
  
  DIC methodologies by learning and applying cutting‑edge physical design techniques.
• Collaborate across teams including multi‑die design, packaging, and sign‑off to achieve project milestones
• Support 3
  
  DIC experimental and 2.5
  
  DIC production programs
  , focusing on PNR flow bring‑up, debugging, and optimization using Cadence, Synopsys, Mentor, and tool flows
  .

Interested candidates meeting the above criteria are encouraged to apply against the job posting or by sending their updated resume to