Mixed-Signal Verification Engineer

We are seeking a highly motivated Mixed‑Signal Verification Engineer III to support verification of analog and mixed‑signal IP integrated within digital‑on‑top SoC environments. Reporting to the Analog Design Team Manager, this individual contributor role will lead development and execution of verification strategies for complex power, clocking, and mixed‑signal subsystems prior to tape‑out. The ideal candidate brings strong expertise in System Verilog, UVM methodologies, and behavioral modeling, along with hands‑on experience verifying analog IP in large‑scale SoC environments.

• Lead mixed‑signal verification activities for analog IP blocks using System Verilog and UVM‑based methodologies.
• Develop scalable digital‑on‑top verification environments and test benches incorporating behavioral models for analog IP including PLLs, LDOs, oscillators, DC/DC converters, and related circuitry.
• Translate analog and mixed‑signal specifications into comprehensive verification plans, assertions, coverage models, and checkers.
• Create and maintain behavioral models using System Verilog real‑number modeling (RNM) and/or Verilog‑AMS for efficient system‑level simulation.
• Execute regression testing, analyze failures, and debug issues across analog, digital, and mixed‑signal domains.
• Verify configuration, calibration, monitoring, protection, and fault‑handling interfaces between analog IP and digital control logic.
• Collaborate closely with analog designers, digital verification engineers, and system architects to ensure verification completeness and tape‑out readiness.

• Develop high‑level functional and behavioral models optimized for large‑scale SoC simulation while maintaining key analog performance characteristics.
• Define modeling assumptions, validation approaches, and abstraction strategies in partnership with analog design teams.
• Contribute to mixed‑signal co‑simulation methodologies balancing simulation accuracy, runtime efficiency, and model reuse.

• Utilize industry‑standard digital, mixed‑signal, and AMS simulation and verification tools.
• Apply coverage‑driven and assertion‑based verification methodologies to ensure robust design validation.
• Participate in design and verification reviews while adhering to established regression, version control, and documentation practices.
• Identify and implement opportunities for workflow automation and verification flow improvements.

• Work independently on complex verification assignments while providing mentorship to junior engineers.
• Contribute verification expertise during IP architecture, integration, and design reviews.
• Proactively identify technical risks, communicate issues effectively, and drive resolution across cross‑functional teams.

• Bachelor’s or Master’s degree in Electrical Engineering or a related technical discipline.
• 6+ years of experience in mixed‑signal and/or digital IC verification.
• Strong proficiency with System Verilog and UVM‑based verification methodologies.
• Hands‑on experience developing behavioral models using Verilog‑AMS and/or System Verilog real‑number modeling.
• Experience verifying analog and mixed‑signal IP within digital‑on‑top SoC environments.

• Familiarity with power management and clocking architectures including bandgaps, PLLs, LDOs, oscillators, and DC/DC converters.
• Experience with coverage‑driven verification, assertions, and formal verification concepts.
• Exposure to automotive, industrial, or safety‑critical semiconductor development environments.
• Experience with scripting, automation, or AI‑assisted verification workflows.