VLSI Design Verification Manager - Slingshot ASIC Team

## VLSI Design Verification Manager - Slingshot ASIC Team Apply locations:
Ft. Collins, Colorado, United States of America:
Bloomington, Minnesota, United States of America:
Chippewa Falls, Wisconsin, United States of America time type:
Full time posted on:
Posted Yesterday job requisition :
1206816

VLSI Design Verification Manager - Slingshot ASIC Team This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.
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* Who We Are:

** Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next.

We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
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* Job Description:

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** Job Description
** Hewlett Packard Enterprise is seeking a
** VLSI Design Verification Manager
** to lead design verification for
** Slingshot

TM networking ASICs**, the high‐performance interconnect used in HPE’s flagship HPC and AI supercomputers. HPE Slingshot is a modern, Ethernet‐based interconnect purpose‐built for large‐scale HPC and AI clusters, delivering industry‐leading bandwidth, low latency, adaptive routing and scalability for demanding workloads. In this role, you will lead a team of design verification engineers responsible for ensuring functional correctness and quality of complex networking ASICs used in NIC and switch products.

You will own verification methodology, execution quality, and sign‐off readiness, while growing and mentoring engineers across a range of experience levels.

This role manages a team of approximately
** 8-15 engineers** (TCP
01–TCP
05) and sits at the intersection of deep technical leadership, people development, and program execution.
** Responsibilities
* ** Provide leadership and direction for a team responsible for all phases of
** pre‐silicon design verification**, including verification planning, testbench development, coverage closure, regression management, and sign‐off reviews.
* Define, own, and evolve
** design verification methodology**, ensuring consistent, high‐quality verification practices across block, subsystem, and full‐chip scopes.
* Ensure development of robust
** System Verilog/UVM‐based environments**, including stimulus, scoreboards, checkers, assertions, and functional coverage.
* Drive regression health, failure triage, root‐cause isolation, and closure of design issues in close collaboration with logic design and architecture teams.
* Manage project deliverables, schedules, and staffing to meet program milestones and quality goals.
* Recruit, mentor, and develop engineers; set performance expectations and support career growth across junior through senior levels.
* Identify and drive opportunities for process improvement, reuse, automation, and efficiency in verification workflows.
* Communicate verification status, risks, and readiness clearly to management and cross‐functional partners.## ##
** Education and Experience Required
*** Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
* Typically
** 10+ years of experience in VLSI design verification**, with strong hands‐on background in pre‐silicon DV.## ##
** Required Knowledge and Skills
*** Strong understanding of
** System Verilog and UVM‐based verification methodologies**.
* Demonstrated
** technical leadership
** in design verification. (e.g., DV technical lead, block or project verification owner)
* Ability to lead engineers through influence, technical credibility, mentorship, and clear communication.
* Experience with verification planning, coverage‐driven verification, regression management, and sign‐off readiness.
* Proficiency with DV workflows using…