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Senior Physical Design Engineer - LPU

Job in Aurora, Arapahoe County, Colorado, 80012, USA
Listing for: NVIDIA
Full Time position
Listed on 2026-05-31
Job specializations:
  • Engineering
    Systems Engineer, Automation Engineering, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self‑driving cars that can understand the world.

Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

Join NVIDIA and become part of a team advancing the frontiers of AI technology! As we lead innovation in AI and accelerated computing, we seek a Senior Physical Design Engineer to contribute to our outstanding progress in chip design. At NVIDIA, you’ll collaborate with extraordinary talent and thrive in an environment that values diversity, collaboration, and remarkable accomplishments.

What You'll Be Doing
  • Full‑Flow Ownership:
    Responsible for Synthesis, floor planning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.
  • Cross‑Functional Optimization:
    Partner with IP, Front‑End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
  • Tapeout Execution:
    Lead design closure in collaboration with IP, PnR, Sign‑off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
  • Methodology Innovation:
    Architect data‑driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.
What We Need To See
  • B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years of industry experience delivering full‑flow physical design for large‑scale, high‑performance SoCs at advanced process nodes.
  • Full‑Flow Execution:
    Proven track record of driving designs through the complete RTL‑to‑GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification.
  • Low‑Power Expertise:
    Deep understanding of low‑power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi‑voltage domain architectures.
  • Clock & Timing Mastery:
    Expert‑level proficiency in advanced CTS methodologies, clock tree synthesis, and sign‑off timing analysis (MCMM STA) using complex constraints.
  • PPA Optimization:
    Demonstrated ability to implement aggressive power, performance, and area optimization techniques, and identify reduction opportunities across the entire physical design cycle.
  • Sign‑off & Integrity:
    Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure.
  • DFT & Block‑Level Integration:
    Skilled in employing best‑known methods to optimize and handle DFT structures within block‑level physical design implementations.
  • EDA Tool Proficiency:
    Expert‑level command of industry‑standard tool suites for end‑to‑end physical design flows.
  • Automation & Innovation:
    Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward‑looking ability to integrate AI‑driven optimizations for enhanced design efficiency.
  • High‑Speed IP Integration:
    Specialized experience in the physical design of blocks and partitions containing high‑speed Ser Des IPs, such as PCIe, CXL, C2C, and Die‑to‑Die interfaces a plus.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 16, 2026.

Applications for this job have been accepted until March 16, 2026. This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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Position Requirements
10+ Years work experience
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