Senior Manager, Analog IP Design , Analog IP Design

Overview:
Annapurna Labs, an Amazon company, is seeking an exceptional leader to build and lead our next‑generation internal Analog IP design team. This unique opportunity involves creating a world‑class analog design center from the ground up to develop critical IP blocks that power our custom silicon products, including Graviton (server CPUs) and Nitro (networking/security accelerators).

• Build the team:
  Recruit, hire, and develop a world‑class analog/mixed‑signal design team from the ground up. Define the org structure, roles, and growth path.
• Define the IP strategy:
  Own the analog IP roadmap across all Annapurna Labs products. Evaluate build‑vs‑buy decisions and drive internal capability development.
• Drive execution:
  Lead the full design cycle from architecture through silicon validation — spec, schematic, layout, simulation, tapeout, and bring‑up.
• Collaborate cross‑functionally:
  Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.
• Set technical direction:
  Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.
• Innovate at scale:
  Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.
• Engage with leadership:
  Communicate strategy, progress, and risk to senior leadership. Influence the overall silicon roadmap with analog capabilities and constraints.

Work at the intersection of analog design and hyperscale cloud infrastructure, build a team and IP portfolio that directly impacts AWS’s competitive edge, have access to leading‑edge process nodes and world‑class foundry partnerships, collaborate with top‑tier silicon architects, system designers, and software engineers, and see your designs deployed at unprecedented scale — millions of instances worldwide.

• B.Sc. in Electrical Engineering.
• 15+ years of hands‑on analog/mixed‑signal design experience in advanced CMOS nodes (7 nm and below).
• 5+ years of proven engineering management experience, including building and scaling teams.
• Deep expertise in one or more: high‑speed Ser Des/PHY, PLL/DLL, data converters, LDOs/power management, or I/O interfaces.
• Track record of successful tapeouts and silicon bring‑up in volume production.
• Experience with design methodologies for IP portability and reuse across multiple process nodes.
• Strong understanding of semiconductor physics, device modeling, and process technology.

• Experience with die‑to‑die interfaces (UCIe, HBI) or advanced packaging (2.5D/3D).
• Experience with integrated voltage regulators (IVR) for high‑performance compute.
• Experience leading analog IP development in a hyperscaler or large semiconductor company.
• Familiarity with GPIO design for multi‑standard (LPDDR, PCIe, CXL) compatibility.
• Background in developing reusable IP platforms with configurable/parameterized architectures.
• Experience in cloud/data center silicon or high‑performance computing.
• Strong publication record or patents in analog IC design.

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