Principal Infinity Fabric Verification Engineer

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We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

The Infinity Fabric transport layer verification team is looking for a primary pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across AI, Client, Server, Graphics, and Semi-Custom markets. Our growing team is in need of additional experienced senior engineering to help us enhance our configurable testbench and to mentor junior engineers.

The preferred candidate will have proven experience verifying complex design blocks at the IP or SoC level using System Verilog/UVM or related technologies. He or she should be comfortable creating and executing on test plans in collaboration with design and verification colleagues in a metric-focused environment. And a track record of technically leading verification teams in the execution of silicon design and verification closure.

• Create project schedules and staging plans for new feature development
• Develop and enhance System Verilog / UVM-based test benches to verify new features for AI & Server products.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
• Lead a team of verification engineers to execute in the verification of new features within project schedules.
• Communicate and interact with project management to stage new feature development per the larger Infinity Fabric development
• Mentor verification engineers.

• Extensive industry experience is preferred.
• Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, or I/O subsystems
• Architected and developed complex verification environments in System Verilog or C++ and infrastructure, including scripting using Perl, Ruby, Make, or the likes.
• Have personally implemented verification tests, sequences, scoreboards, checkers, assertions and coverage groups.
• Led groups in complete verification process including closing coverage and tracking bug rates
• Exposure to RTL design, software development, formal verification, or other related domains.
• Excellent communication, management, and presentation skills.

• Master’s degree in related discipline preferred

Austin, TX

This role is not eligible for visa sponsorship.>

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.