Principal IPQA Automation Engineer

Overview

Arm teams develop groundbreaking Silicon demonstrators which embed the latest Arm Compute Sub-System IP (Intellectual Property) and other outsourced IP. We are looking for a creative and hardworking principal engineer to join the IP Qualification team to verify these third‑party IPs before they are embedded in SoC. Such TPIP include foundation IP (e.g. standard‑cells, SRAM), NVM (e‑fuse, anti‑fuse), PLL, sensors, and sub‑system interfaces (controller + PHY) like LPDDR, USB, Ethernet or PCIe.

You will join a newly formed team in Austin and collaborate with multiple other groups inside Arm.

• Lead the installation and verification of all TPIP EDA models to ensure they align with Arm SoC design flow requirements.
• Ensure models adhere to DFX (Design for Test, Debug, Reliability, Manufacturing and Yield) requirements as defined by Arm.
• Use the IP Qualification flow and major EDA tools to analyze deviations and share findings with SoC design teams for review.
• Report deviations to IP providers for updates.
• Propose and lead the implementation of new checks to improve coverage and ensure compliance of receivables with SoC flow and DFX.

• At least 18 years of post‑master degree work experience in IP design or verification and/or implementation and signoff.
• At least two of the following experiences:
  Functional verification of IP blocks/subsystems, RTL code linting and CDC/RDC verification, scan stitching, ATPG and pattern simulation, synthesis, low‑power (UPF) physical implementation and verification, timing and power signoff, power grid integrity checks, scripting for task automation (Shell, TCL, Python or other), strong interpersonal skills, interface IP protocol verification, boundary scan integration (IEEE‑1149), SI/PI checks at chip/package level, functional safety and cyber security requirements.

• Functional verification of IP blocks/subsystems.
• RTL code linting and CDC/RDC verification.
• Scan stitching, ATPG and pattern simulation.
• Synthesis, low‑power (UPF) physical implementation and verification, timing and power signoff.
• Power grid integrity (electro‑migration, voltage‑drop) and physical checks.
• Scripting for task automation with Shells (e.g. Bash), TCL, Python or any other language.
• Excellent interpersonal skills, strong initiative and openness in engaging and learning various IP and the SoC reference design flow.
• Experience in Verify‑IP usage for interface IP protocol verification.
• Boundary scan integration (IEEE‑1149).
• SI/PI (signal/power integrity) checks at chip/package level.
• Functional safety and cyber security requirements.

Private medical insurance (employee and family), 20 days annual leave, 20‑day sabbatical every four years, supplementary pension and reduced working hours.

Salary range: $241,100‑$326,100 per year.

If you need an adjustment or accommodation during the recruitment process, please email  All accommodation requests are treated with confidentiality.

Arm’s approach to hybrid working supports both high performance and personal wellbeing. Groups/teams determine their own hybrid patterns based on work and team needs.

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.