DFT Design Engineer

Overview

We are seeking a senior DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our semiconductor products. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations. The position focuses on achieving optimal test coverage, minimizing defect escape rates, and reducing overall test costs while maintaining design integrity and performance targets.

The successful candidate will architect, implement, and optimize test strategies from RTL development through production manufacturing and collaborate with cross-functional teams to deliver robust DFT solutions for complex SoCs.

This role combines deep technical expertise in digital design with specialized knowledge of test methodologies to ensure silicon products meet the highest quality standards for high-volume manufacturing. The candidate will work at the intersection of design and test with teams across architecture, verification, physical design, and manufacturing.

• Design & Development:
  Develop logic design, RTL coding, and simulation for DFT implementations.
• Provide DFT timing closure support and generate test content for manufacturing delivery.
• Implement various DFx content including SCAN, MBIST, and BSCAN methodologies.
• Apply strategies, tools, and methods to write and generate RTL and structural code for DFT integration.

• Architecture &
  
  Collaboration:
  
  Define architecture and microarchitecture features for blocks, subsystems, and SoCs.
• Collaborate on DFT design including TAP, SCAN, MBIST, BSCAN, processor monitors, and in-system test/BIST.
• Integrate DFT blocks into functional IP and SoC while supporting customer integration requirements.

• Optimization & Verification:
  Optimize logic design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals.
• Review verification plans and drive DFT design verification to achieve architecture specifications.
• Ensure design features are verified correctly and implement corrective measures for failing RTL tests.

• Manufacturing & Production Support:
  Develops HVM (High Volume Manufacturing) content for rapid bring-up and production ramp on ATE (Automatic Test Equipment).
• Collaborate with post-silicon and manufacturing teams for silicon verification and debug support.
• Drive high test coverage through structural and IP-specific tests to achieve quality and DPM objectives.
• Document learnings and improvement requirements for design and validation processes.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or related field with 4+ years of industry experience or Master's degree with 3+ years of industry experience.

Technical Requirements

• 5+ years of hands-on experience with DFT (Design for Test) methodologies.
• 5+ years of experience with Array Test including MBIST (Memory Built-In Self-Test).
• Experience in RTL coding, simulation, and verification.
• Experience in semiconductor manufacturing test processes and ATE systems.

Preferred Qualifications

• Expert-level proficiency in Tessent DFT tool suite.
• Advanced expertise in Prime Time, specifically with DFT constraints and timing analysis.
• Experience with additional DFT tools and methodologies.
• Knowledge of advanced test compression techniques and fault models.
• Experience with SoC-level DFT integration and customer support.
• Background in post-silicon validation and debug.
• Familiarity with industry test standards and protocols.
• Experience in test cost optimization and DPM improvement initiatives.

• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary
  
  Location:
  
  US, Arizona, Phoenix
• Additional Locations: US, California (Santa Clara), US, Massachusetts (Beaver Brook), US, Oregon (Hillsboro), US, Texas (Austin)

At the Data Center Group (DCG), we deliver Xeon-based solutions and custom x86-based products for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter includes strategy, product management, ecosystems, and collaboration with partners to drive innovation.