Power Management Design Engineer

Company Qualcomm Technologies, Inc.

Job Area Engineering Group, Engineering Group > ASICS Engineering

General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next‑generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Candidate will be responsible for designing and developing next generation power control systems. Candidate will be working on ASICs based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of the VLSI development cycle like architecture, micro‑architecture, RTL design along with interactions with verification, synthesis & PD teams for design convergence.

• 5 to 8 years of strong experience in digital front end design for ASICs
• Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
• Familiar with UPF and power domain crossing
• Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
• Experience in low power design methodology and clock domain crossing designs
• Experience in Spyglass Lint/CDC checks and waiver creation
• Experience in formal verification with Cadence LEC
• Understanding of full RTL to GDS flow to interact with DFT and PD teams
• Expertise in Perl, TCL language
• Expertise in post‑Si debug is a plus
• Good documentation skills
• Should possess good communication skills to ensure effective interaction with Engineering Management and team members
• Should be self‑motivated with good teamwork attitude and need to function with minimal guidance or supervision

• Digital design and development (RTL) working in close collaboration with multi‑site leads across US and India
• Developing the micro‑architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
• Design and implement defined tasks independently
• Work in close coordination with Systems, Verification, SoC team, SW team, PD & DFT teams to achieve the goals
• Analyze reports/waivers or run various tools:
  Spyglass, 0‑in, DC‑Compiler, Prime Time, synthesis, simulation, etc.

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

$ – $. The above pay scale reflects the broad minimum to maximum pay range for this job code for the location for which it has been posted. Salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants.

Not Applicable

Full‑time

Other