RTL Design Engineer

As an Interconnect RTL Design Engineer, you will be part of the Systems team focused on next-generation interconnects targeting high-end mobile, automotive, networking, and enterprise markets. You will take part in specification, microarchitecture and RTL design of high-performance, energy-efficient interconnects. You will also be considering functional safety aspects of the design that include exploration, analysis and implementation.

As an RTL Design Engineer, you would be accountable for one or more functional units of the Interconnect while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. Typical accountabilities include:

• Understanding the high-level specification and requirements of functional units of Interconnect products.
• Define the Micro-architecture for a unit and develop Verilog RTL logic design for the unit
• Using power aware design methodologies, analyzing early results from tools like RTL Power Pro.
• Collaborate with verification team on the test plan development for the blocks and verification closure
• Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets

• BS/MS in Electrical and/or Computer Engineering with between 4-8 years of experience.
• Good understanding of all stages of the design cycle: initial concept, specification, implementation, verification, documentation and support.
• Experience with System Verilog RTL design, coupled with design synthesis.
• Experience with lint/CDC/RDC, SVA, and at least one formal tool (e.g., Jasper/VC Formal) for protocol and liveness properties.
• Comfortable with synthesis/STA (Design Compiler/Genus, Prime Time/Tempus) and debug across sim, emulation, and silicon.
• Good interpersonal and teamwork skills. Clear, data-driven communication.

• Experience with interconnect and bus architecture. Interconnect concepts: virtual channels, arbitration, QoS, wormhole/credit flow control, deadlock/livelock avoidance, packetization/flits, PCIe etc.
• Knowledge of AMBA protocols (e.g. AMBA5 CHI, AMBA5 AXI, ACELite, AMBA5 APB etc.) is a plus.
• Experience with power aware RTL design methodologies and analysis tools. Low-power design (UPF/CPF), power/clock gating, retention, DVFS.

With offices around the world, Arm is a diverse organization of dedicated, creative, and very hardworking engineers. By enabling a multifaceted, inclusive, meritocratic, and open workplace, where everyone can grow and succeed, we encourage our people to share their unrivaled contributions to Arm's success in the global marketplace.

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email  To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation.

Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.

Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the team’s needs. Details…