Director of Physical Design

Overview

Company Overview Ambiq's mission is to enable intelligence everywhere by delivering the lowest power semiconductor solutions. Ambiq is a pioneer and a leading provider of ultra-low-power semiconductor solutions based on our proprietary and patented sub- and near-threshold technologies. With the increasing power requirements of artificial intelligence (AI) computing, our customers are relying on our solutions to deliver AI to edge environments.

Our hardware and software innovations fundamentally deliver a multi-fold improvement in power consumption over traditional semiconductor designs without expensive process geometry scaling. We began in 2010 by addressing the power consumption challenges of battery-powered devices at the edge, where they were most pronounced. As of the beginning of 2025, we've shipped more than 280+ million units worldwide.

Our innovative and fast-moving teams of design, research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin), Taiwan (Hsinchu), China (Shanghai and Shenzhen), and Singapore. We value relentless technology innovation, a deep commitment to customer success, collaborative problem-solving, and an enthusiastic pursuit of energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies.

We encourage and nurture an environment that fosters growth and opportunities to work on complex, meaningful, and challenging projects, creating a lasting impact and shaping the future of technology. Join us on our quest for enabling billions of intelligent devices. The intelligence everywhere revolution starts here.

This role will be on-site 5 days a week in NW Austin.

We’re seeking an accomplished Director of Physical Design to lead and scale our physical implementation organization for next-generation ultra-low-power microcontroller (MCU) products. This is a strategic, high-impact leadership role responsible for driving the physical design roadmap, ensuring world-class PPA (power, performance, area), and delivering robust silicon for high-volume embedded applications.

You will guide a multidisciplinary team across physical implementation, methodology, and signoff, partnering closely with architecture, RTL design, analog/mixed‑signal, verification, and product engineering to bring innovative MCU solutions to market.

Leadership & Strategy

• Define and execute the physical design strategy for low‑power MCU product lines.
• Build, mentor, and lead a high‑performing global physical design team.
• Establish best‑in‑class methodologies for low‑power, high‑reliability physical implementation.
• Drive continuous improvement in design flows, automation, and signoff quality.

Physical Implementation

• Oversee full‑chip and block‑level physical design including:
• Floor planning
• Power planning and low‑power architecture implementation
• Clock tree synthesis (CTS)
• Place & route (P&R)
• Timing closure
• Physical verification (DRC/LVS)
• EM/IR and rel‑ability signoff
• Ensure optimal PPA tradeoffs tailored for ultra‑low‑power MCU architectures.

Cross-Functional Collaboration

• Partner with architecture and RTL teams to influence early design decisions.
• Work closely with analog/mixed‑signal teams to integrate mixed‑signal IP into SoCs.
• Collaborate with product engineering and operations to ensure manufacturability and yield.
• Interface with foundries to align on technology capabilities, PDK updates, and design rules.

Execution & Delivery

• Own physical design schedules, resource planning, and risk management.
• Ensure first‑silicon success through rigorous signoff and validation processes.
• Drive tape‑out readiness and post‑silicon debug support.

Required

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in physical design for complex SoCs, with at least 5 years in leadership roles.
• Proven track record of delivering multiple chips to production.
• Deep expertise in:
• Low‑power design techniques (multi‑Vt, power gating, DVFS, retention,…