Physical Design Engineer

Job Title:
Physical Design Engineer (5–10+ Years Experience)

Number of Positions: 10

Location: USA

Experience: 5–10+ Years

Domain: VLSI / Semiconductor / ASIC Physical Design

We are seeking an experienced Physical Design Engineer with 5–10+ years of hands-on experience in ASIC physical design. The candidate will be responsible for end-to-end block/full-chip physical design activities from RTL2

GDSII/Netlist2

GDSII, ensuring high-quality, STA, SI, EMIR and PV (DRC/LVS/ERC/ANT)-clean layouts.

• Drive full-chip SoC/Block level physical design from RTL2
  
  GDSII/Netlist2
  
  GDSII
• Perform top-level/sub-system/Block synthesis, floor planning, partitioning, and hierarchical integration
• Develop and implement full-chip/Block level power planning and power grid strategies
• Manage block integration, timing budgeting, and interface closure
• Execute and optimize placement, CTS, routing, and post-route flows at full-chip level
• Handle top-level congestion, SI, noise, IR drop, and EM closure
• Perform and drive physical verification closure (DRC/LVS/ERC/ANTENNA)
• Manage ECO flows including full-chip and block-level ECOs
• Collaborate closely with RTL, synthesis, STA, DFT, packaging, and verification teams
• Support tapeout planning, signal checks, and final delivery milestones
• Build and enhance automation scripts and PD flows

Note: Strong formatting requested; bolds converted to tags. Text preserved as provided.

• Strong experience in full-chip SoC implementation
• Deep expertise in:
  • Top-level floor planning and partitioning
  • Chip-level power planning and multi-voltage domains
  • Hierarchical and flat implementation flows
  • Timing budgeting and interface timing closure
  • CTS and clock architecture at SoC level
  • Congestion and routing optimization
• Strong knowledge of:
  • MMMC timing setup and closure
  • OCV/AOCV/POCV, SI and Crosstalk analysis
  • Multi-voltage and low-power flows (UPF/CPF)