Analog Design Engineer
Listed on 2026-02-16
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Engineering
Systems Engineer, Electronics Engineer, Electrical Engineering, Hardware Engineer
Job Title:
Analog Design Layout Engineer
Duration of project: 12 months or longer with possible extensions
Hiring Manager’s notes:
Client is looking for a specialist who can handle the constraints of 3D, 16nm transistor technology to build high-performance analog blocks.
An Analog Physical Design (Layout) Engineer working on advanced semiconductor manufacturing technologies.
Looking for someone who can physically draw the layout of analog circuits on a chip using TSMC’s 16nm FinFET process node.
The layout must be created for specific, sensitive analog building blocks including Bias, Opamp, LDO, and Bandgap.
Bias Circuits:
Used to set operating points for other circuits.
LDO (Low-Dropout Regulators):
Power management circuits that regulate voltage.
Bandgap References:
Circuits that provide a precise, temperature-independent voltage.
Cadence Virtuoso:
The standard tool for this type of layout.
FinFET Layout Rules:
Managing fin counts, 3D structures, and strict orientation.
Physical Verification:
Debugging DRC, LVS, and Antenna errors.
Reliability Analysis:
Managing Electromigration (EM) and IR drop (voltage drop) in 16nm
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