Tech Lead, and Power Analysis

About Neurophos

The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.

Join us and shape the future of computing!

We are seeking an experienced Lead for Performance and Power Analysis (PPA) to establish and drive our modeling infrastructure for performance characterization and power/energy optimization. This leadership role combines deep technical expertise in hardware modeling with team leadership responsibilities. You will build the PPA modeling team, define methodologies for performance and power simulation, and drive critical architectural decisions through data-driven analysis of our novel optical computing platform.

Location:

Austin, TX or San Mateo, CA. Full-time onsite position.

• Lead the PPA modeling team (4+ engineers) focused on performance and power analysis
• Architect and implement performance models with discrete-event timing and cycle-accurate simulation
• Develop power and energy modeling frameworks for optical engines, SRAM arrays, and digital logic
• Define PPA analysis methodologies and establish modeling best practices
• Drive performance optimization through bottleneck identification and architectural trade‑off analysis
• Collaborate with the architecture team on the performance characterization of novel compute blocks
• Build and maintain a trace-driven simulation infrastructure for independent performance analysis
• Develop power models for optical components, photonic devices, and opto-electronic interfaces
• Work with silicon design teams to validate models against RTL and post‑layout results
• Mentor modeling engineers and establish team development practices
• Present PPA results to the executive team and drive architecture decisions

• MS or PhD in Computer Engineering, Electrical Engineering, or Computer Science (or BS with equivalent experience)
• 10+ years of experience in performance modeling and power analysis for CPUs, GPUs, or accelerators
• Proven experience building and leading technical teams (3+ years of management experience)
• Deep expertise in discrete-event simulation, cycle‑accurate modeling, and performance analysis
• Strong background in power modeling frameworks (McPAT, Cacti, or custom methodologies)
• Expert‑level C++ programming with a focus on performance‑critical simulation code
• Experience with trace‑driven simulation and performance bottleneck analysis
• Track record of shipping performance models that drove silicon design decisions
• Excellent communication skills and ability to present technical results to diverse audiences
• Experience with performance characterization of ML workloads on specialized hardware

• Experience with GPU performance modeling or shader core analysis
• Background in accelerator architectures (TPU, NPU, DSP) or domain‑specific processors
• Knowledge of memory system modeling (HBM, DRAM controllers, cache hierarchies)
• Familiarity with optical computing, photonics, or analog computing paradigms
• Experie…