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ASIC Design Verification Engineer; Santa Clara, CA

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Qualcomm
Full Time position
Listed on 2026-05-18
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer, Electronics Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: ASIC Design Verification Engineer (Santa Clara, CA)

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. This is the Invention Age – and this is where you come in as a ASIC Design Verification Engineer. The team is responsible for the complete verification lifecycle, from system‑level concept to tape‑out and post‑silicon support.

The responsibilities of the position include comprehensive pre‑silicon test planning for digital power IP, testbench development using System Verilog‑UVM and other advanced verification methodologies, coverage development, assertion model development and formal verification (property checking). The role also involves learning and deploying power‑aware UPF verification flow and methodology, and developing automation to improve verification efficiency.

Qualifications
  • Minimum 3 years of DV experience using UVM/assertion based verification technologies
  • Experience verifying complex SOC or SOC subsystems
  • Experience with caches and DDR memory protocol verification
  • Experience with using memory verification VIP’s
  • Exposure to DDR PHY
  • Exposure to firmware/driver development using C++
  • Exposure with multiple successful tapeouts from conception to post‑silicon debug
  • Exposure to formal verification
  • Exposure to PASIM simulations
  • Exposure to performance and power verification
Skill Proficiency

UVM, System Verilog, assertion, C++, Python

Technology

DDR, Cache, SOC

Minimum Qualifications
  •  Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
  •  Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
  •  PhD in Science, Engineering, or related field
Pay Range And Other Compensation & Benefits

$ – $. The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation. In addition, we offer a competitive annual discretionary bonus program, opportunity for annual RSU grants, and a highly competitive benefits package designed to support your success at work, at home, and at play.

Equal

Opportunity

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e‑mail disability‑ or call Qualcomm’s toll‑free number. Upon request, reasonable accommodations will be provided to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

EEO

Employer

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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