Senior CPU Performance Architect

As a CPU Performance Architect, you will play a pivotal role in shaping the future of Intel’s cutting‑edge CPU designs, driving innovation across high‑performance computing and extreme low‑power products. This position offers the unique opportunity to be at the forefront of technological advancements, defining and delivering architecture specifications that directly impact Intel’s success and industry leadership. Your contributions will influence the performance, scalability, and efficiency of CPUs that serve diverse market segments, from enterprise solutions to edge computing devices.

Through collaboration with cross‑functional teams, you will invent novel microarchitectural approaches, overcome bottlenecks, and refine designs to meet stringent constraints and evolving demands.

• Develop and drive end‑to‑end CPU microarchitecture specifications for highly optimized, modular, and scalable CPUs based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.
• Evaluate feasibility trade‑offs, explore, and define new approaches and novel microarchitectures for CPUs.
• Model CPU performance and power characteristics, and analyze the bottlenecks of current performance features on workloads that reflect CPU future usage.
• Collaborate with architects, design, verification, and validation engineers during the execution of projects.
• Deliver definition of new microarchitecture and identify mitigations for issues that arise during feature implementation to improve the overall design of CPUs and overcome bottlenecks and constraints.
• Participate in debugging and fixing performance miscorrelation between RTL and/or silicon results against the performance model.

• Master’s degree with at least 10+ years of experience, or PhD with dissertation in CPU performance, and 6+ years experience on a high‑performance, high‑frequency ARM or x86 CPU performance team.
• At least 8+ years of continuous work within cycle‑accurate C++ CPU performance simulators.
• Candidate must have experience in designing high‑performance CPUs and should be an expert in at least one or more CPU domains such as Branch Prediction, Fetch/Decode, Rename/Allocation, Reservation Stations/Execution, Memory Subsystem, or Prefetchers and its interactions with Uncore. Experience in debugging microarchitecture and simulation issues. Strong background in microarchitecture/RTL/logic development, and proven ability to resolve complex problems using analytical and technical skills.

• Background in CPU microarchitecture and experience modeling features in a cycle‑accurate performance simulator.
• Experience in microarchitecture exploration and identifying new features that provide IPC improvements across the CPU.
• Experience from inception to real silicon: pathfinding, definition, correlation with RTL, and post‑silicon performance debugging and tuning.
• Experience with performance scenarios/use cases and KPI/workloads.
• Advanced skills with Object‑Oriented Programming (C++, STL) and scripting languages.
• Ability to write assembly and craft tests to evaluate and debug microarchitectural features.
• Ability to read/debug performance issues in RTL.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

This role is a Position of Trust. You must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks.