Senior Design Verification Engineer

Position: Senior Staff Design Verification Engineer
About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Custom Solutions partners with the world's most advanced technology companies-including leading hyperscalers, cloud data center operators, and telecom providers-to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed Ser Des (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies-all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics.

In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from architecture and design through validation and production-to solve complex technical challenges that directly impact how billions of people experience technology, ensuring that every design meets the exacting specifications and performance requirements that our customers depend on to power their mission-critical infrastructure.

What You Can Expect

* Define and drive comprehensive verification strategies and test plans for complex SoCs, subsystems, or IP blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon built in advanced process nodes (3nm, 2nm)

* Architect and implement sophisticated UVM-based verification environments including test benches, reference models, scoreboards, monitors, coverage models, and protocol checkers to ensure exhaustive verification of assigned blocks

* Develop and execute comprehensive test plans encompassing directed tests, constrained-random scenarios, and coverage-driven verification to verify functional correctness, performance requirements, and error handling across all design features

* Own end-to-end verification closure including code coverage, functional coverage, and assertion coverage analysis, working with design teams to resolve coverage gaps and achieve 100% coverage goals with documented waivers

* Debug complex simulation failures using systematic root-cause analysis techniques, correlating RTL behavior with specifications, and partnering with designers to identify and resolve design issues efficiently

* Collaborate closely with logic designers, architects, DFT engineers, and physical design teams throughout the development cycle on micro-architecture reviews, test plan development, timing closure support, and gate-level simulation execution

* Drive verification methodology improvements by developing reusable verification components (VKITs), creating automation scripts for regression management and coverage analysis, and establishing best practices that enhance productivity across global verification teams

* Support multiple verification platforms including RTL simulation, emulation/FPGA prototyping, and post-silicon validation, ensuring test portability and maintaining verification infrastructure across platforms

* Integrate and validate third-party VIPs (Verification IP) and vendor models for industry-standard protocols, ensuring proper configuration and effective utilization within the verification environment

* Present verification progress, coverage results, and quality metrics to stakeholders through milestone reviews, cross-functional design reviews, and verification sign-off meetings, maintaining clear documentation throughout the verification cycle

* Coach and mentor junior verification engineers when necessary to develop their technical…