Principal AI Hardware Architect

Principal AI Hardware Architect — Hardware/Software Co-Design

Grow with us

Location:

Austin, TX

The Architect Who Closes the Gap. The Engineer Who Makes Silicon Inevitable.

Most chip programs are full of brilliant people who never quite speak the same language.

Researchers build ambitious AI models. Silicon teams build powerful hardware. Infrastructure teams wire it all together. And somewhere in the space between those three worlds — in the handoffs, the assumption gaps, the untranslated requirements — massive performance dies quietly on the floor.

As Principal AI Hardware Architect, you will own the most consequential technical contract in the company: the binding agreement between what AI workloads demand, what software systems can express, and what custom silicon can physically deliver.

This is not a support role. This is not a liaison role.

• Workload-to-Architecture Translation – translate modern AI workloads into concrete hardware requirements that actually matter.
• Hardware/Software Co-Design Leadership – bridge model engineering, AI infrastructure, and silicon architecture teams.
• Performance Model Ownership – build and own the projection systems that guide compute investments, memory hierarchy decisions, and feature prioritization.
• Real Workload Validation – profile real workloads on real and future platforms, find bottlenecks, and feed findings into the next hardware and software cycle.
• Strategic Technical Translation – align people who think in different languages and ground every product decision in real workloads.

• AI/ML Systems Depth – understand modern AI architectures, inference systems, quantization strategies, deployment constraints, and workload behavior on silicon.
• Silicon Architecture Fluency – experience with processor, accelerator, or custom silicon architectures, compute pipelines, memory hierarchies, on‑chip interconnects, performance trade‑off analysis.

• 12+ years of industry experience across AI, systems, or silicon.
• Proven experience at the intersection of hardware and intelligent compute systems.
• Hardware/software co‑design leadership across full product cycles.
• Demonstrated performance modeling expertise – analytical, simulation, or cycle‑approximate.
• Track record of influencing architectural and product decisions across multiple technical organizations.
• Exceptional written communication and technical specification ability.
• Strong Python and C++ skills.

• Experience with custom silicon, accelerators, or advanced hardware platforms.
• Prior involvement in ISA definition, memory hierarchy design, or accelerator roadmap decisions.

• Salary range depends on location and qualifications.
• Location:
  
  Austin, Texas.
• Health benefits – choice of three medical plan options and a dental plan option with company credits equal to the cost that Ericsson pays toward the premiums.
• 401(k) Plan – automatic 3% company contribution and matching contributions up to 4% of eligible pay, with company credits for basic life insurance and disability coverage.
• Paid time off – minimum 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually.
• Paid maternity leave of up to 16 weeks and parental or adoption leave of 6 weeks at 100% pay.
• Additional benefits – financial wellness programs, educational assistance, matching gifts, and recognition programs.

Ericsson is proud to be an Equal Opportunity employer, learn more.